The present invention pertains to multiple central processing unit (CPU) controlled real-time systems and more particularly to a scheme for increasing the bandwidth for each CPU of a multi-processor configuration for accessing a commonly shared resource.
Computerized control of telecommunication systems is known in the art. Modern telecommunication systems require vast amounts of processing power in order to provide the varied telecommunication functions commonly in use. Distributed processing or load sharing among CPUs is now common place in large real time systems. The telecommunications industry is no exception to this rule.
In a distributed processing system, CPUs exchange information via a common resource or memory. In this way, the system's tasks may be divided among the available CPUs. Such a system also avoids multiple CPUs initiating the same task by granting access to the common resource or memory to only one CPU at a particular time.
Therefore, when several CPUs attempt to access the common resource or memory, a selection arrangement must allow only one CPU to access the common resource or memory at a time. This hardware is termed contention resolution or arbitration circuitry. One such arbitration controller is shown in U.S. Pat. No. 4,394,728, for an invention entitled Allocation Controller Providing For Access of Multiple Common Resources By A Duplex Plurality Of Central Processing Units. This patent was issued on July 19, 1983, to the same assignee as that of the present application. U.S. Pat. No. 4,394,728, is hereby incorporated by reference. U.S. Pat. No. 4,395,753, issued on July 26, 1983, also teaches this arbitration scheme. This Patent is antitled Allocation Controller Providing For Access of Multiple Common Resources by a Plurality of Central Processing Units. This patent is also incorporated by reference.
The above mentioned Patents teach an arbitration circuit which alternately grants access to a common resource to a CPU within one of two subgroups. Each subgroup contains sixteen CPUs. The arbitration scheme employed in these Patents is to alternate granting request to the common resource between the two subgroups. In addition, arbitration within a subgroup of sixteen CPUs was handled on a rotational bases (i.e. CPU0 first; CPU1 second; . . . CPU15 then CPU0 again).
The operation of this arbitration scheme may best be understood by referenced FIG. 1. FIG. 1 depicts the arbitration scheme employed by the circuitry of the above mentioned U.S. patents. FIG. 1 shows two CPU subgroups, each subgroup including sixteen CPUs. The designation for CPU0 of subgroup 0 is repeated for explanation purposes. Assume that all CPUs of both subgroups are requesting access to the common resource. Assume further that CPU0 of subgroup 0 is the first to be allocated access to the common resource, the arbitration circuitry then gives control to subgroup 1, but advances the CPU indicator to the next CPU within the group. As a result, CPU1 in subgroup 1 is allocated access to the common resource next. This is indicated by the arrow from CPU0, subgroup 0 to CPU 1, subgroup 1. Next, since this arbitration circuitry advances the CPU count and allocates access to the other group of CPUs. CPU2 in subgroup 0 is the next CPU to be allocated control to common resource (this is indicated by the arrow from CPU1, subgroup 1 to CPU2, subgroup 0). CPU3 in subgroup 1 is the next CPU to be allocated access to the common resource.
As can be seen from FIG. 1, every other CPU in each subgroup is not granted access to the common resource. This is due to the grant of access "walking" in between CPU subgroups, but always being advanced. This configuration was designed to handle telecommunication events which typically occur at the rate of 10 milliseconds per event. In situations where there is CPU contention for the common resource (i.e. many CPUs simultaneously requesting) and when events occur on an average of approximately 10 millisecond intervals typically true CPU contention, the CPU contentions are easily resolved within this time frame, since the available bandwidth is 666 nsec. This arbitration logic was designed in this fashion and worked well to allow up to 96 duplex processors access to the common resource for telecommunication functions which occurred at approximately 10 millisecond rate.
Public policy requires telecommunication functions including telephone service to operate 24 hours a day continuously without a disruption of service. Therefore, highly reliable telecommunication systems are required. In the above mentioned Patents, each CPU or processor has associated with it local memory. This local memory contains the operating instructions for each CPU. If this local memory becomes mutilated, the processors may not operate efficiently, if at all.
For a telecommunication system outage, no telephone services are provided. Such conditions must be quickly rectified. During outages in the system which employs the above mentioned Patents, reloading the local memory of a CPU from the common memory requires approximately 1 hour. This means that those telecommunication functions and telephone subscribers served by this processor are potentially without service for up to 1 hour.
Improvements were made to the system software which loaded processors whose local memory had become mutilated. This system software is able to reload a processor's local memory very quickly by constantly generating requests for access to the common resource with a frequency of request of approximately 1 request per 666 nanoseconds. As a result, the "walking" phenomenon referred to above in FIG. 1 was observed. That is, certain CPUs were quickly loaded while others were virtually completely ignored for access to the common resource.
For the duration of the reloading process, each CPU of each subgroup was constantly generating a request for access to the common resource. Due to the alternating rotational scheme employed by the arbitration circuitry of the above mentioned Patents, the CPU access bandwidth (frequency of access through the arbitration logic) was found to be insufficient to accommodate the 666 nanosecond bandwidth of 32 constantly requesting CPUs.
A fully equipped group of CPUs along with associated arbitration circuitry includes up to 17 printed wiring cards (PWCs). Since there are two copies of each CPU and arbitration circuit operating in duplex, a fully equipped CPU group (2 subgroups) included up to 34 PWCs. Each CPU group includes two subgroups (subgroup 0 and subgroup 1) as mentioned above. A fully equipped telecommunication system may include up to three processor groups. As a result, up to 96 duplex processors may be generating requests for access to the common resource.
Originally, it was believed that a complete redesign of the arbitration circuitry would be required to accommodate this fast reloading procedure. In addition, it was believed that each of the printed wiring cards would require redesign and relayout. The redesign and relayout functions are extremely costly and require considerable amounts of engineering time and effort.
It, therefore, is an object of the present invention to allow constant access to a common resource by a large number of CPUs, thereby increasing the bandwidth of the CPU/common resource interface, while requiring minimal circuit and engineering changes to the circuitry shown in the above mentioned Patents.